As a package structure facilitating miniaturization, high functionality and high performance of semiconductor integrated circuit chips, there has been proposed a grid array package such as WL-CSP (Wafer Level Chip Scale Package) or BGA/LGA.
Typically, when a package such as WL-CSP/BGA/LGA or the like is mounted on a printed circuit board (hereinafter, referred to as a “PCB substrate”), in order to pass wirings between lands corresponding to balls on the PCB substrate, wiring pitches get narrow and the cost of the PCB substrate increases.
In particular, in the case of WL-CSP, the relationship between a chip size and a ball size has an opposite relationship. That is, when the chip size is reduced, the ball pitch is narrowed, which results in increase in the PCB substrate cost. Conversely, when the ball pitch is widened, the chip size is increased, which results in increase in the chip cost.